Hardware
- Putting the "You" in CPU – cpu.land
- What every programmer should know about memory, Part 1 [LWN.net]
- Modern Microprocessors - A 90-Minute Guide!
- MIT 6.004 Computation Structures, Spring 2017 - YouTube
CPU can the thought as an interpreter or even a JIT compiler as it actually executes microcode for each instruction.
Instruction pipeline: Fetch, Decode, Execute, Writeback.
Caches
- Data cache
- Instruction cache
- TLB
AArch64
L1 cache has 2 units: one for the data cache, one for the instruction cache. L2 is usually for data only.
SIMD is done through FPR (floating point registers).
Notes
RISC-V is a modular ISA, you can choose which instructions you're interested in.